1. Field of the Invention
The present invention relates to the fabrication of semiconductor memory devices of the type including trench memory storage capacitors, and more particularly, to a semiconductor memory device where the surface area of the trench memory storage capacitor is increased.
2. Background Art
U.S. Pat. No. 4,557,395, issued Mar. 25, 1986 to Shibata, entitled METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE HAVING TRENCH MEMORY CAPACITOR discloses a method of manufacturing a semiconductor memory device having a trench memory capacitor. First masks are formed on an element forming region of a semiconductor substrate formed of the element forming region and an element isolation region. A film formed of a different material from that of the first masks is deposited and it etched by anisotropic dry etching to leave second masks around the first mask. The semiconductor substrate is selectively etched using the first and second masks as an etching mask so as to form a first groove in the element isolation region. An insulation film is buried in the first groove. A portion of the first mask, formed at least above memory capacitor forming regions in the element forming region, is removed by etching, thereby forming a third mask on a portion excluding the, memory capacitor forming region. The semiconductor substrate is selectively etched by using the second and third masks and the insulation film buried in the first groove as an etching mask so as to form second grooves in the respective memory capacitor forming regions. A distance between the first and second grooves is defined by the second masks in a self-alignment manner. A capacitor electrode is formed in the second grooves through a gate insulation film.
U.S. Pat. No. 4,905,065, issued Feb. 27, 1990 to Selcuk et al. entitled HIGH DENSITY DRAM TRENCH CAPACITOR ISOLATION EMPLOYING DOUBLE EPITAXIAL LAYERS describes a new double-epitaxial structure for isolating deep trench capacitors with 1 .mu.m or less spacing is disclosed. The structure comprises a thin, lightly doped upper epitaxial layer on top of a thicker and more heavily doped bottom epitaxial layer. The low resistivity bottom epitaxial layer is intended to isolate trench capacitors of any depth. The high resistivity upper epitaxial layer is used for the CMOS periphery and can be selectively doped to achieve a near uniform concentration to isolate trench capacitors in the core region surrounding the capacitors. Isolation between deep trenches at 1 .mu.m spacing has been demonstrated to be applicable for 4 Megabit and greater DRAM integration levels.
U.S. Pat. No. 4,859,622, issued Aug. 22, 1989 to Eguchi, entitled METHOD OF MAKING A TRENCH CAPACITOR FOR DRAM discloses a structure wherein two or three trenches are formed in a silicon substrate facing the trenches. An oxide film for insulation is formed on a surface of the conductive layer facing the trenches. The trenches are filled with polysilicon, and the conductive layer and the polysilicon constitute a capacitor through the oxide film. Since this capacitor has two or three trenches, an effective area sufficiently large for increasing a capacitance value of the capacitor can be obtained without increasing the plane area of the device. The conductive layer and the polysilicon are connected to aluminum interconnection layers through a silicide layer, so as to be connected to other integrated circuits.
U.S. Pat. No. 4,737,470 issued Apr. 12, 1988 to Bean, entitled METHOD OF MAKING THREE DIMENSIONAL STRUCTURES OF ACTIVE AND PASSIVE SEMICONDUCTOR COMPONENTS relates to a three dimensional semiconductor structure formed in a semiconductor substrate wherein electrical components, both active and passive, are formed on the substrate surface as well as in grooves formed in the substrate at an angle and extending to the surface. The substrate surface is designed to lie in a predetermined crystallographic plane of the substrate material and the grooves extend in a predetermined crystallographic direction from said plane, this being accomplished by orientation dependent etching.
U.S. Pat. No. 4,650,544, issued Mar. 17, 1987 to Erb et al., entitled SHALLOW GROOVE CAPACITOR FABRICATION METHOD discloses a structure wherein a shallow capacitor cell is formed by using conventional integrated circuit processes to build a substrate mask having sublithographic dimensions. Multiple grooves, or trenches, are etched into the substrate using this mask. The capacitor dielectric layer and plate are then formed in the grooves.
U.S. Pat. No. 4,849,854, issued Jul. 18, 1987 to Eguchi, entitled SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME teaches a structure wherein two or three trenches are formed in a silicon substrate, and a conductive layer is formed in the silicon substrate facing the trenches. An oxide film for insulation is formed on a surface of the conductive layer facing the trenches. The trenches are filled with polysilicon, and the conductive layer and the polysilicon constitute a capacitor through the oxide film. Since this capacitor has two or three trenches, an effective area sufficiently large for increasing a capacitance value of the capacitor can be obtained without increasing the plane area of the device. The conductive layer and the polysilicon are connected to aluminum interconnection layers through a silicide layer, so as to be connected to other integrated circuits.
U.S. Pat. No. 4,920,065, issued Apr. 24, 1990 to Chin et al., entitled METHOD OF MAKING ULTRA DENSE DRAM CELLS relates generally to dynamic random access semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells.
U.S. Pat. No. 5,013,680, issued May 7, 1991 to Lowrey et al., entitled PROCESS FOR FABRICATING A DRAM ARRAY HAVING FEATURE WIDTHS THAT TRANSCEND THE RESOLUTION LIMIT OF AVAILABLE PHOTOLITHOGRAPHY discloses a process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process includes the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidistantly-spaced isolation trenches in a silicon substrate; filing the isolation trenches with insulative material; creation of a hard-material mask consisting of strips that are 11/2F. in width, separated by spaces that are 1/2F in width, that is used to etch a matrix of storage trenches; angled implanatation of an N-type impurity in the storage trench walls; another anisotropic etch to deepen the storage trenches; deposition of a capacitor dielectric layer; deposition of a protective polysilicon layer on top of the dielectric layer; removal of the dielectric layer and the protective polysilicon layer at the bottom of each storage trench with a further anisotropic etch; filling the storage trenches with in situ-doped polysilicon and planarization down to the substrate level; creation of an access gate on opposite sides of each storage trench.